Hierarchical Bayesian Inference Implementation in Neuromorphic Hardware
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2023-06-14
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en
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Neuromorphic hardware is a novel computer architecture based on a computational model
of biological neurons that uses sparse, event-driven, distributed and stochastic computation
to provide superior energy efficiency compared to traditional von Neuman architecture. In
neuroscience, Bayesian inference is used as a theoretical framework for modelling brain processing
and there are numerous models that attempt to explain how Bayesian Inference can
be computed in a biologically plausible neural network. These models can be used as a basis
to investigate efficient neuromorphic algorithms for Bayesian Inference. After brief survey
of spiking neural network models for Bayesian Inference, the Hierarchical Bayesian Inference
model by [12] is selected for implementation on the Loihi neuromorphic chip. The Hierarchical
Bayesian Inference model uses Winner-take-all circuits as a building block to represent categorical
distribution, which are further stacked in a hierarchical fashion to extract more complex
features from input data and learn to cluster input by Spike-Timing Dependend Plastisity
(STDP). Findings suggest that the integer precision of Loihi, paired with hardware restrictions
on the size of neuron parameters proves to be insufficient to accurately represent conditional
probabilities. Additionally, in the WTA circuit implementation the simulation time required
to resolve a winner grows with the number of excitatory neurons, therefore the largest WTA
circuit bottlenecks the entire model even when smaller circuits have already converged to a
stationary distribution. As a consequence of the lack of synaptic precision and the poor probability
approximation of larger WTA circuits, the current neuromorphic implementation fails to
reproduce the results of Guo et al [12] on the MNIST benchmark for unsupervised classification
of handwritten digits.
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Faculteit der Sociale Wetenschappen